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Formal equivalence checking
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#	Item
11	Datasheet Formality and Formality Ultra Equivalence Checking for DC Ultra and Design Compiler Graphical Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-18 15:15:30 Formal methods Physical design SystemVerilog Synopsys Formal verification Verilog Formal equivalence checking Signoff Electronic engineering Electronic design automation Hardware description languages
12	Transition Invariants Andreas Podelski Andrey Rybalchenko Max-Planck-Institut f¨ur Informatik Add to Reading List Source URL: www.verisoft.de Language: English - Date: 2013-04-11 05:48:57 Equivalence relation Model checking Temporal logic Invariant Termination analysis Mathematical proof Formal verification Mathematics Theoretical computer science Applied mathematics
13	Combinational Equivalence Checking Using Satisfiability and Recursive Learning João Marques-Silva Add to Reading List Source URL: eprints.soton.ac.uk Language: English - Date: 2009-12-08 13:36:52 Boolean algebra Formal methods Logic in computer science Electronic design automation NP-complete problems Boolean satisfiability problem Conjunctive normal form Binary decision diagram Formal equivalence checking Theoretical computer science Mathematics Applied mathematics
14	The Human ECO Compiler Steve Golson Add to Reading List Source URL: www.trilobyte.com Language: English - Date: 2004-03-21 14:53:16 Formal equivalence checking Integrated circuit design Application-specific integrated circuit Logic synthesis Place and route Register-transfer level High-level synthesis Netlist Wire wrap Electronic engineering Electronic design automation Engineering Change Order